Integrated circuits can include modules that perform a variety of functions. Each of the foregoing modules may access a shared memory in the performance of its functions. The shared memory may comprise, for example, a dynamic random access memory (DRAM). A DRAM controller controls access to the DRAM.
The functions can send requests for memory accesses to the DRAM controller over a DRAM access bus supporting multiple functions. The functions may operate at different clock speeds from one another as well as the memory. Additionally, some of the functions may operate in real time. Arbitration and real time scheduling are used when more than one function requests access during a particular time interval. The requests are serialized over the bus.
A DRAM can comprise any number of banks, although four is typical. Each bank comprises any number of rows. Before a memory access to a particular location, the bank comprising the particular location is electrically pre-charged. After pre-charging the bank, the particular row and location can be accessed. The time for electrically pre-charging the row is usually a significant fraction of this total time. Additionally, once the particular row is accessed, other memory locations in the same row can also be accessed without requiring additional pre-charge operations. Accordingly, accesses to a memory row can be characterized by a large overhead, and smaller marginal costs.
Real time scheduling can take advantage of the foregoing qualities of the DRAM by scheduling burst transactions for the functions. In a burst transaction, the functions access a large number of consecutive memory locations that are typically on the same row of one bank, or on one row of each of multiple banks. Burst transactions are easier to implement with functions that tend to access consecutive locations within each row of the DRAM.
However, certain functions may not tend to access consecutive locations of the DRAM. One example of a function that may not tend to access consecutive locations of the DRAM is a motion compensation function in a video encoder or decoder. In standards such as Advanced Video Coding (AVC), also known as MPEG-4 Part 10 AVC, or ITU-T H.264, predicted pixels may be predicted from blocks of reference pixels in a reference frame that are as small as 2×2 or as large as 21×21. One block of reference pixels can straddle multiple rows and banks of DRAM. Additionally, reference pictures can be stored in memory in a variety of ways. Accordingly, the memory locations that store the reference pixels can tend to be non-consecutive.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.